$135,000 - $160,000.
Employer description & source details
Circuit Design & Optimization: Perform transistor-level circuit design, simulation, and optimization for high-performance analog and mixed-signal blocks. Block-Level Architecture: Design and develop precision references and bias circuits, operational amplifiers, comparators, LDO regulators, oscillators, timing circuits, data converter support circuits, and power management/isolation-related analog circuits. Layout & Physical Design Support: Support IC floorplanning and work closely with layout engineers to ensure robust analog layout implementation. Silicon Validation: Analyze silicon measurement results, conduct lab evaluation, and drive necessary design improvements. Qualification & Reliability: Support product qualification, characterization, and reliability testing activities. Education: M.S. or Ph.D. in Electrical Engineering (or B.S. with equivalent, demonstrated technical expertise). Technical Fundamentals: Deep understanding of CMOS device physics and analog circuit fundamentals. EDA Tools: Hands-on experience with Cadence Virtuoso, Spectre, and standard circuit simulation tools. Process & Reliability: Practical knowledge of semiconductor process technologies and reliability considerations. Soft Skills: Excellent technical documentation skills, strong verbal communication, and the ability to work effectively in a cross-functional, global team environment. Experience with GaN (Gallium Nitride) device applications and driver design. Experience with isolated IC design methodologies and high-voltage power management circuits. The expected annual pay range for this position is $135,000 - $160,000. This position is also eligible for bonus opportunities. Please note that the final offer amount will be dependent on geographic location, applicable experience, and skillse