Employer description & source details
Serve as technical authority for IC and SiP packaging across multiple products and programs. Own package architecture and technology roadmap, aligned with product, cost, and scalability goals. Lead chiplet-based packaging strategies, including UCIe, silicon interposers, and advanced RDL. Perform and guide hands-on package design and physical layout, including critical structures for High-speed SerDes/PHY (PCIe, CXL), LPDDR5, UCIe, and Other multi-gigabit interfaces. Define substrate stack-ups, materials, bump/RDL architectures, and DFM guidelines for advanced nodes. Drive SI/PI, thermal, mechanical, and reliability trade-offs at the system and package levels. Lead external engagement with OSATs, foundries, and key suppliers for technology development and manufacturing readiness. Influence product roadmap, risk management, and investment decisions through technical insight. Establish scalable design methodologies, best practices, and reusable packaging flows. BSEE or MSEE (PhD a plus) in Electrical Engineering, or related field. Minimum of 10+ years of experience with extensive IC packaging expertise for SoCs, ASICs, or memory products. Deep hands-on expertise in Flip-Chip BGA (FCBGA) and System-in-Package (SiP), RDL, silicon interposers, and chiplet architectures (UCIe) Strong understanding of electrical, mechanical, thermal, and reliability design trade-offs, Advanced packaging materials and substrate technologies, Design-for-Manufacturing (DFM) and yield optimization Demonstrated ability to operate autonomously, make high-impact decisions, and execute in a startup environment. Technical leadership of multiple end-to-end packaging programs, from early architecture through high-volume production. Proven experience with high-speed SerDes package development, including PC
Extracted skills: operations