Employer description & source details
Astera Labs is redefining the connectivity that powers rack-scale AI infrastructure, and analog design is at the heart of it. As a Principal Analog Design Engineer, you will architect and design the high-performance analog and mixed-signal circuits that anchor our SerDes, PHY, and high-speed I/O — the silicon building blocks that move data at the speed AI demands. Your work directly shapes the performance, power, and reliability of products deployed in the world's most advanced data centers. This is a high-impact, hands-on role at a hyper-growth company purpose-built for AI connectivity. You will own designs from concept through silicon bring-up, set the technical bar for the analog team, and mentor engineers as we scale. If you want your circuits to enable the next generation of AI compute, this is where that happens. Architect and design high-speed analog and mixed-signal circuits including PLLs, LDOs, references, high-speed SerDes building blocks, ADCs/DACs, and clocking. Drive circuit design from specification and architecture through schematic, layout supervision, and verification across PVT corners. Develop robust designs in advanced FinFET process nodes with attention to power, area, and performance trade-offs. Lead silicon bring-up, characterization, and debug, partnering with validation and product engineering to root-cause and resolve issues. Define and execute test plans to correlate silicon performance against design targets. Set analog design methodology, review standards, and best practices across the team. Partner cross-functionally with digital, physical design, systems, and architecture teams to deliver full-chip solutions. Mentor and guide junior engineers, elevating the technical capability of the analog organization. MS or PhD in Electrical Engineeri