Employer description & source details
Quadric is building a revolutionary new processor-based SoC architecture. As a Staff SoC Design Engineer, you will get in on the ground floor as a key member of our chip design team, contributing across all stages of the SoC design and integration cycle. In this role, you will help define the SoC architecture, own subsystem development, integrate third-party IP, and drive PPA optimization to bring our next-generation platform to life. SOC SUBSYSTEM DEVELOPMENT & IP INTEGRATION Own SoC-level subsystem development and seamless integration with third-party IP (such as NoC, PCIe/UCIe interfaces, DDR, Security, etc.). Contribute directly to the definition of the SoC architecture by deeply understanding its application requirements. Package designs for customer releases and rapidly iterate based on customer feedback. Own Power, Performance, and Area (PPA) optimization strategies at the SoC level. Apply low-power digital design techniques to optimize hardware efficiency. Contribute to timing closure across the full product lifecycle, spanning front-end, back-end, and final tapeout stages. Balance single-stream latency against scaled throughput performance. Within your first 6–12 months, you'll: Independently own SoC subsystem development and drive measurable PPA improvements. Develop an in-depth understanding of the architecture and software interfaces, enabling you to debug complex issues across the full SW/HW stack. Successfully package and deliver design releases for customer evaluation and integration. BS, MS, or Ph.D. in Electrical Engineering, Computer Engineering, or a related field. Minimum 5+ years of hands-on SoC/ASIC front-end design and integration experience. Proficiency in SystemVerilog or Verilog. Strong background in computer architecture, low-power digital des
Extracted skills: c++, security