Employer description & source details
CScale is building the interconnect for gigawatt-scale AI. As AI scale-up moves toward deployments spanning thousands of accelerators and dozens of racks, the network needs to deliver high bandwidth, predictable low latency, and continuous communication. CScale is building integrated optical interconnect designed for this new scale, enabling accelerators to work together like a single, much larger computer. But at this scale, performance is only part of the challenge. Optical failures are inevitable, and the system needs to keep running. CScale is designing the interconnect for continuity. Lasers will fail. Compute shouldn’t. The ambition is simple: Build AI interconnect you can take for granted. CScale came out of stealth in September 2026 with $145 million in Series C funding, bringing total funding to $188 million. Build the integrated plan across SoC and chiplet/multi-die design, hardware, firmware, software, foundry, packaging, test and QA. Physical design: Drive floorplan, bump map, timing and power convergence, IR/EM and signoff, and coordinate netlist, constraint, IP-view and package handoffs across FE, PD, analog and packaging. Dependencies: Maintain a cross-team dependency tracker with owners and dates, resolve blockers, and escalate with options and a recommendation. Working knowledge of the full SoC flow: architecture, IP integration, RTL, verification (UVM, formal, emulation), physical design, STA, DFT, tapeout, post-silicon validation and qualification.
Extracted skills: operations