Employer description & source details
Astera Labs is hiring a Principal Design Verification Engineer to own functional verification of our high-speed SerDes/PHY IP — the connectivity engine powering rack-scale AI infrastructure. You will architect verification environments, drive coverage closure, and ensure first-pass silicon success on the analog/digital boundary that defines next-generation AI systems. This is a high-impact, hands-on role at the heart of Astera Labs' hyper-growth story. You'll partner directly with PHY analog/mixed-signal designers, digital architects, and SoC integration teams to verify multi-Gbps SerDes blocks that ship into the world's most advanced AI platforms, including UALink, UCIe, PCIe Gen 6/Gen 7, and Ethernet-based connectivity products. Architect UVM-based verification environments for SerDes/PHY IP, including PMA, PCS, and PHY-MAC interface layers Define verification plans, coverage models, and sign-off criteria for high-speed serial link blocks Drive methodology decisions across analog/mixed-signal co-simulation, gate-level simulation, and emulation flows Develop SystemVerilog/UVM testbenches, sequences, scoreboards, and reference models for multi-Gbps SerDes lanes Execute functional, performance, and corner-case verification across equalization, CDR, training, and link bring-up scenarios Lead coverage analysis and closure, debug failures with designers, and drive regressions to clean tape-out Physical Layer & Protocol Verification Verify PHY behavior against industry specifications including PCIe Gen 6/Gen 7, UALink, UCIe, and Ethernet PHY standards Model and validate channel behavior, link training state machines, and analog handoff scenarios Partner with analog/AMS designers on Real Number Modeling (RNM) and behavioral models for SerDes blocks Mentor junior DV engineers
Extracted skills: python